Intel has notified its partners about the specs of its up-and-coming Alderwood chipsets, which support Socket T, the 775 LGA socket that's in the pipeline, so to speak. The Alderwood, the document seen by the INQ says, has a new memory controller hub (MCH) backbone, and as expected these support DDR-2 dual channel memory.
The architecutre supports asynchronous and isochronous data, with dedicated internal pipelines, and Intel is touting better electricals with optimised ball out and an extra "bypass" (eek) enabled.
The MCH uses a 1210 flip chip ball grid array, while the different ICHs in the shape of ICH6, ICH6R, ICH6W and ICH6RW use a 609 micro BGA package.
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