• It seems, K9 will have an integrated DDRII controller
• Processor will feature speculative branching (up to 8 branches), and
probably some rollback cache in case a branch is predicted wrong...
• Processor will probably have 3 (!) fully-fledged õ87 blocks, 3 SSE2
and 2 ALU blocks. Decoders will be capable of organizing them by
three (FPU + SSE2 + ALU) for maximum performance.
• K9 will possibly utilize AMD’s old patent, escribing integrated Peltier
• Processor might have several buffers, a kind of L0 cache. For
example, a 4Kb buffer will precede and follow FPU for making its
operation (SSE2, 3DNow) continuous.
• K9 might also support L3 cache for commented code. I.e. decoder
will be capable of acting right in L3 inserting comments into special
• Pipeline will probably feature 15 ALU stages, 20 FPU stages.
• I-cache and decoder will perform at double speed.
• AMD might situate L3 cache on crystal using 1T-SRAM.
• Hyper Transport II – expected to be something like Octal Data
Rate (Yellowstone) with about 1GHz carrier clock. As a result
throughput will reach 25Gb/s in 16x16 configuration.
• Interprocessor protocol (MOESI) will be updated and improved.
• The very fast bus will provide a very interesting feature of sharing
free executive units between two processors. I.e. if the first has FPU
loaded and the second has it free, then the latter can handle
requests from the decoder of the former.
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