Looking at the memory roadmaps, the next question to ask is whether the 400 MHz bus speed is effectively the end of the FSB frequencies. With Intel already announcing the 800 MHz bus interface for the upcoming Prescott processor and DDR technology heading into the direction of 533 MHz even in DDR-I format, AMD could find themselves in a difficult position in that the older 32 bit processors may deliver equal performance to what the Hammer/Opteron family is capable of doing. With the latter, the problem is that the memory controller is an integral component of the CPU and has been named as one of the culprits for the delayed release. This could also mean that the memory controller does not scale as well with a higher memory frequency but keep in mind that this is pure speculation.
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